1. Field
Exemplary embodiments of the present invention relate to a semiconductor design, and more particularly, to a semiconductor integrated circuit and a semiconductor system including the semiconductor integrated circuit.
2. Description of the Related Art
In this specification, the technology of the present invention is described by taking a semiconductor memory device as an example.
In general, a semiconductor memory device, such as a Dynamic Random Access Memory (DRAM) device, is fabricated by stacking and packaging a plurality of semiconductor chips, or die, to acquire greater capacity than before from the same area. Herein, a semiconductor memory device where one semiconductor chip is stacked and packaged is referred to as a single-die package (SDP), and a semiconductor memory device where two semiconductor chips are stacked and packaged is referred to as a dual-die package (DDP). A semiconductor memory device where four semiconductor chips are stacked and packaged is referred to as a quad-die package (QDP).
Meanwhile, whether to drive the stacked and packaged semiconductor chips is controlled based on a chip selection signal applied from an external controller to each semiconductor chip.
FIG. 1A illustrates a semiconductor system including a single-die package according to prior art, and FIG. 1B illustrates a semiconductor system including a dual-die package according to prior art. FIG. 1C illustrates a semiconductor system including a quad-die package according to prior art.
Referring to FIG. 1A, the semiconductor system 10 includes a first external controller 11 and first to fourth single-die packages 13, 15, 17 and 19. The first external controller 11 generates first to fourth chip selection signals CS0#, CS1#, CS2# and CS3#. Meanwhile, the first to fourth single-die packages 13, 15, 17 and 19, each having a semiconductor chip (not shown), are driven, respectively, in response to the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3#.
Herein, the first external controller 11 independently controls which of the semiconductor chips included in the first to fourth single-die packages 13, 15, 17 and 19 is driven by independently applying the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3# through the first to fourth channels CS_CH#0, CS_CH#1, CS_CH#2 and CS_CH#3, respectively. Typically, the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3# are low active signals.
The first to fourth single-die packages 13, 15, 17 and 19 each include one pad CS_PIN0 for receiving the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3#, respectively. Since the first to fourth single-die packages 13, 15, 17 and 19 are under the control of the first external controller 11, the first to fourth single-die packages 13, 15, 17 and 19 transfer/receive various signals to/from the first external controller 11. For example, the semiconductor chip included in each of the first to fourth single-die packages 13, 15, 17 and 19 is driven according to the corresponding chip selection signal CS0#, CS1#, CS2# or CS3#, and performs a write operation for storing a data (not shown) applied from the first external controller 11 in response to a command and an address (not shown) that are transferred from the first external controller 11, or performs a read operation for providing a stored data (not shown) to the first external controller 11.
Referring to FIG. 1B, the semiconductor system 20 includes a second external controller 21, a first dual-die package 23, and a second dual-die package 25. The second external controller 21 generates the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3#. The first dual-die package 23 independently drives two semiconductor chips (not shown) included therein in response to the first and second chip selection signals CS0# and CS1#. Likewise, the second dual-die package 25 independently drives two semiconductor chips (not shown) included therein in response to the third and fourth chip selection signals CS2# and CS3#.
Herein, the second external controller 21 independently controls whether to drive the two semiconductor chips included in each of the first and second dual-die packages 23 and 25 by independently applying the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3# through the first to fourth channels CS_CH#0, CS_CH#1, CS_CH#2 and CS_CH#3, just as the first external controller 11 illustrated in FIG. 1A does.
Moreover, the first and second dual-die packages 23 and 25 each include two pads CS_PIN0 and CS_PIN1 for receiving two chip selection signals CS0# and CS1# or CS2# and CS3#, respectively. Meanwhile, since the first and second dual-die packages 23 and 25 are under the control of the second external controller 21, the first and second dual-die packages 23 and 25 transfer/receive various signals to/from the second external controller 21. For example, the two semiconductor chips included in each of the first and second dual-die packages 23 and 25 are driven based on the corresponding chip selection signals of the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3#, and the semiconductor chips perform a write operation for storing a data (not shown) applied from the second external controller 21 or perform a read operation for providing a stored data (not shown) to the second external controller 21 in response to a command and an address (not shown) transferred from the second external controller 21.
Referring to FIG. 1C, the semiconductor system 30 includes a third external controller 31 for generating the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3# and a quad-die package 33 which independently drives four semiconductor chips (not shown) included therein in response to the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3#.
Herein, the third external controller 31 independently controls whether to drive the four semiconductor chips included in the quad-die package 33 by independently applying the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3# through the first to fourth channels CS_CH#0, CS_CH#1, CS_CH#2 and CS_CH#3, just as the first external controller 11 illustrated in FIG. 1A does.
Moreover, the quad-die package 33 further includes four pads CS_PIN0, CS_PIN1, CS_PIN2 and CS_PIN3 for receiving the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3#. Meanwhile, since the quad-die package 33 is under the control of the third external controller 31, the quad-die package 33 transfers/receives various signals to/from the third external controller 31. For example, the four semiconductor chips included in the quad-die package 33 are driven based on the corresponding chip selection signals CS0#, CS1#, CS2# and CS3#, and perform a write operation for storing a data (not shown) applied from the third external controller 31 or perform a read operation for providing a stored data (not shown) to the third external controller 31 in response to a command and an address (not shown) transferred from the third external controller 31.
The known semiconductor systems 10, 20 and 30 having the above structures, however, have the following drawbacks.
First, the number of channels for applying chip selection signals increases as the number of semiconductor chips included therein increases. For example, the first external controller 11 requires the first channel CS_CH#0 to control the first single-die package 13, and the second external controller 21 requires the first and second channels CS_CH#0 and CS_CH#1 to control the first dual-die package 23. The third external controller 31 requires the first to fourth channels CS_CH#0, CS_CH#1, CS_CH#2 and CS_CH#3 to control the quad-die package 33. Accordingly, when 8, 16, or 32 semiconductor chips are stacked and packaged in a semiconductor package, an external controller requires as many channels as the number of the semiconductor chips. Considering that integration degree of semiconductor devices is increasing, an increase in the number of channels is a notable limitation.
Furthermore, the semiconductor packages 13, 15, 17, 19, 23, and 33 require as many pads as the number of the semiconductor chips included therein. For example, the first single-die package 13 includes one pad CS_PIN0 for receiving the first chip selection signal CS0#, and the first dual-die package 23 includes two pads CS_PIN0 and CS_PIN1 for receiving the first and second chip selection signals CS0# and CS1#. The quad-die package 33 includes four pads CS_PIN0, CS_PIN1, CS_PIN2 and CS_PIN3 for receiving the first to fourth chip selection signals CS0#, CS1#, CS2# and CS3#. When 8, 16 or 32 semiconductor chips are stacked and packaged, there are as many pads as the number of the semiconductor chips. However, as stack and packaging technology advances, that is, as the number of semiconductor chips that are stacked and packaged increases, an increase in the number of pads is inevitable. Therefore, there is a demand for a method that addresses the concern of the increasing area used for the pads.